--alt_u_div DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=7 WIDTH_Q=7 WIDTH_R=4 denominator numerator quotient remainder --VERSION_BEGIN 18.0 cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_abs 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_divide 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END -- Copyright (C) 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details. --synthesis_resources = lut 32 SUBDESIGN alt_u_div_qse ( denominator[3..0] : input; numerator[6..0] : input; quotient[6..0] : output; remainder[3..0] : output; ) VARIABLE add_sub_0_result_int[1..0] : WIRE; add_sub_0_cout : WIRE; add_sub_0_dataa[0..0] : WIRE; add_sub_0_datab[0..0] : WIRE; add_sub_0_result[0..0] : WIRE; add_sub_1_result_int[2..0] : WIRE; add_sub_1_cout : WIRE; add_sub_1_dataa[1..0] : WIRE; add_sub_1_datab[1..0] : WIRE; add_sub_1_result[1..0] : WIRE; add_sub_2_result_int[3..0] : WIRE; add_sub_2_cout : WIRE; add_sub_2_dataa[2..0] : WIRE; add_sub_2_datab[2..0] : WIRE; add_sub_2_result[2..0] : WIRE; add_sub_3_result_int[4..0] : WIRE; add_sub_3_cout : WIRE; add_sub_3_dataa[3..0] : WIRE; add_sub_3_datab[3..0] : WIRE; add_sub_3_result[3..0] : WIRE; add_sub_4_result_int[5..0] : WIRE; add_sub_4_cout : WIRE; add_sub_4_dataa[4..0] : WIRE; add_sub_4_datab[4..0] : WIRE; add_sub_4_result[4..0] : WIRE; add_sub_5_result_int[5..0] : WIRE; add_sub_5_cout : WIRE; add_sub_5_dataa[4..0] : WIRE; add_sub_5_datab[4..0] : WIRE; add_sub_5_result[4..0] : WIRE; add_sub_6_result_int[5..0] : WIRE; add_sub_6_cout : WIRE; add_sub_6_dataa[4..0] : WIRE; add_sub_6_datab[4..0] : WIRE; add_sub_6_result[4..0] : WIRE; DenominatorIn[39..0] : WIRE; DenominatorIn_tmp[39..0] : WIRE; gnd_wire : WIRE; nose[55..0] : WIRE; NumeratorIn[55..0] : WIRE; NumeratorIn_tmp[55..0] : WIRE; prestg[34..0] : WIRE; quotient_tmp[6..0] : WIRE; sel[31..0] : WIRE; selnose[55..0] : WIRE; StageIn[39..0] : WIRE; StageIn_tmp[39..0] : WIRE; StageOut[34..0] : WIRE; BEGIN add_sub_0_result_int[] = (0, add_sub_0_dataa[]) - (0, add_sub_0_datab[]); add_sub_0_result[] = add_sub_0_result_int[0..0]; add_sub_0_cout = !add_sub_0_result_int[1]; add_sub_0_dataa[] = NumeratorIn[6..6]; add_sub_0_datab[] = DenominatorIn[0..0]; add_sub_1_result_int[] = (0, add_sub_1_dataa[]) - (0, add_sub_1_datab[]); add_sub_1_result[] = add_sub_1_result_int[1..0]; add_sub_1_cout = !add_sub_1_result_int[2]; add_sub_1_dataa[] = ( StageIn[5..5], NumeratorIn[12..12]); add_sub_1_datab[] = DenominatorIn[6..5]; add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]); add_sub_2_result[] = add_sub_2_result_int[2..0]; add_sub_2_cout = !add_sub_2_result_int[3]; add_sub_2_dataa[] = ( StageIn[11..10], NumeratorIn[18..18]); add_sub_2_datab[] = DenominatorIn[12..10]; add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]); add_sub_3_result[] = add_sub_3_result_int[3..0]; add_sub_3_cout = !add_sub_3_result_int[4]; add_sub_3_dataa[] = ( StageIn[17..15], NumeratorIn[24..24]); add_sub_3_datab[] = DenominatorIn[18..15]; add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]); add_sub_4_result[] = add_sub_4_result_int[4..0]; add_sub_4_cout = !add_sub_4_result_int[5]; add_sub_4_dataa[] = ( StageIn[23..20], NumeratorIn[30..30]); add_sub_4_datab[] = DenominatorIn[24..20]; add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]); add_sub_5_result[] = add_sub_5_result_int[4..0]; add_sub_5_cout = !add_sub_5_result_int[5]; add_sub_5_dataa[] = ( StageIn[28..25], NumeratorIn[36..36]); add_sub_5_datab[] = DenominatorIn[29..25]; add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]); add_sub_6_result[] = add_sub_6_result_int[4..0]; add_sub_6_cout = !add_sub_6_result_int[5]; add_sub_6_dataa[] = ( StageIn[33..30], NumeratorIn[42..42]); add_sub_6_datab[] = DenominatorIn[34..30]; DenominatorIn[] = DenominatorIn_tmp[]; DenominatorIn_tmp[] = ( DenominatorIn[34..0], ( gnd_wire, denominator[])); gnd_wire = B"0"; nose[] = ( B"0000000", add_sub_6_cout, B"0000000", add_sub_5_cout, B"0000000", add_sub_4_cout, B"0000000", add_sub_3_cout, B"0000000", add_sub_2_cout, B"0000000", add_sub_1_cout, B"0000000", add_sub_0_cout); NumeratorIn[] = NumeratorIn_tmp[]; NumeratorIn_tmp[] = ( NumeratorIn[48..0], numerator[]); prestg[] = ( add_sub_6_result[], add_sub_5_result[], add_sub_4_result[], GND, add_sub_3_result[], B"00", add_sub_2_result[], B"000", add_sub_1_result[], B"0000", add_sub_0_result[]); quotient[] = quotient_tmp[]; quotient_tmp[] = ( (! selnose[0..0]), (! selnose[8..8]), (! selnose[16..16]), (! selnose[24..24]), (! selnose[32..32]), (! selnose[40..40]), (! selnose[48..48])); remainder[3..0] = StageIn[38..35]; sel[] = ( gnd_wire, (sel[31..31] # DenominatorIn[38..38]), (sel[30..30] # DenominatorIn[37..37]), (sel[29..29] # DenominatorIn[36..36]), gnd_wire, (sel[27..27] # DenominatorIn[33..33]), (sel[26..26] # DenominatorIn[32..32]), (sel[25..25] # DenominatorIn[31..31]), gnd_wire, (sel[23..23] # DenominatorIn[28..28]), (sel[22..22] # DenominatorIn[27..27]), (sel[21..21] # DenominatorIn[26..26]), gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1])); selnose[] = ( (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), ((! nose[52..52]) # sel[31..31]), ((! nose[51..51]) # sel[30..30]), ((! nose[50..50]) # sel[29..29]), ((! nose[49..49]) # sel[28..28]), (! nose[48..48]), (! nose[47..47]), (! nose[46..46]), ((! nose[45..45]) # sel[27..27]), ((! nose[44..44]) # sel[26..26]), ((! nose[43..43]) # sel[25..25]), ((! nose[42..42]) # sel[24..24]), (! nose[41..41]), (! nose[40..40]), (! nose[39..39]), ((! nose[38..38]) # sel[23..23]), ((! nose[37..37]) # sel[22..22]), ((! nose[36..36]) # sel[21..21]), ((! nose[35..35]) # sel[20..20]), (! nose[34..34]), (! nose[33..33]), (! nose[32..32]), ((! nose[31..31]) # sel[19..19]), ((! nose[30..30]) # sel[18..18]), ((! nose[29..29]) # sel[17..17]), ((! nose[28..28]) # sel[16..16]), (! nose[27..27]), (! nose[26..26]), (! nose[25..25]), ((! nose[24..24]) # sel[15..15]), ((! nose[23..23]) # sel[14..14]), ((! nose[22..22]) # sel[13..13]), ((! nose[21..21]) # sel[12..12]), (! nose[20..20]), (! nose[19..19]), (! nose[18..18]), ((! nose[17..17]) # sel[11..11]), ((! nose[16..16]) # sel[10..10]), ((! nose[15..15]) # sel[9..9]), ((! nose[14..14]) # sel[8..8]), (! nose[13..13]), (! nose[12..12]), (! nose[11..11]), ((! nose[10..10]) # sel[7..7]), ((! nose[9..9]) # sel[6..6]), ((! nose[8..8]) # sel[5..5]), ((! nose[7..7]) # sel[4..4]), (! nose[6..6]), (! nose[5..5]), (! nose[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0])); StageIn[] = StageIn_tmp[]; StageIn_tmp[] = ( StageOut[34..0], B"00000"); StageOut[] = ( ((( StageIn[33..30], NumeratorIn[42..42]) & selnose[48..48]) # (prestg[34..30] & (! selnose[48..48]))), ((( StageIn[28..25], NumeratorIn[36..36]) & selnose[40..40]) # (prestg[29..25] & (! selnose[40..40]))), ((( StageIn[23..20], NumeratorIn[30..30]) & selnose[32..32]) # (prestg[24..20] & (! selnose[32..32]))), ((( StageIn[18..15], NumeratorIn[24..24]) & selnose[24..24]) # (prestg[19..15] & (! selnose[24..24]))), ((( StageIn[13..10], NumeratorIn[18..18]) & selnose[16..16]) # (prestg[14..10] & (! selnose[16..16]))), ((( StageIn[8..5], NumeratorIn[12..12]) & selnose[8..8]) # (prestg[9..5] & (! selnose[8..8]))), ((( StageIn[3..0], NumeratorIn[6..6]) & selnose[0..0]) # (prestg[4..0] & (! selnose[0..0])))); END; --VALID FILE